Power density per unit area of a semiconductor chip continues to increase exponentially with each new technology generation, posing a major challenge for thermal management in modern processors. In general, past work has examined architectural details for reducing total consumed chip power, but these techniques alone are insufficient.
Because power density has increased exponentially with Moore's Law, thermal cooling challenges have become a prominent and vexing aspect of computer systems design. Mechanical cooling solutions such as heat sinks and fans remain a possible approach for dealing with thermal issues. However, these solutions are costly and unwieldy.
“Thermal-aware” techniques at the architecture level have gained momentum for optimizing processor performance while also abiding by rapidly worsening thermal constraints. Thermal-aware architecture techniques are related to power-aware techniques, but are a distinct area because thermal-aware designs concern both local hotspot constraints as well as aggregate thermal limits.
The current industry trend has been toward multicore architectures, which provide additional opportunities for dynamic thermal management. Examples of this multicore architecture include devices that have multiple central processing units (CPUs); multiple graphics processing unit (GPUs), multiple digital signal processors (DSPs), multiple field programmable gate arrays (FPGAs), an application processor (Apps processor), or various combinations thereof. Thermal simulations on these hybrid devices show that lateral thermal influence is at least two orders of magnitude slower than self-heating events.
A processor core is an example of a thermal entity, but other examples of thermal entities include other logic blocks, such as video encoders/decoders, memory controllers, I/O blocks, schedulers etc.
In general, processors are designed while keeping thermal constraints in mind. It is common in the industry to assume an equal power distribution among all thermal entities. But this assumption leads to a result that is generally inefficient, because one thermal entity may be in an active state while others may be inactive. It is not possible to immediately allocate power from an inactive thermal entity and distribute it to an active thermal entity and still remain within the thermal constraints.
Hence what is required is a method and apparatus to efficiently allocate power from an inactive thermal entity to an active thermal entity while keeping thermal constraints in mind.